1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device that achieves a uniform current gain due to producing uniform emitter regions, so as to improve reliability of the semiconductor device.
2. Discussion of the Related Art
Generally, a semiconductor device includes a fast bipolar transistor (a field effect transistor in the case of an MOS device) for an arithmetic unit, logic circuits and the like, and a high current bipolar transistor for output circuits. To realize the high current bipolar transistor, an emitter has a wide width. To realize the fast bipolar transistor, an emitter junction and an emitter have thin widths. In the semiconductor device in which the fast bipolar transistor and the high current bipolar transistor are formed in one substrate, current gain of the respective transistors for stable operation is about .+-.30%.
A conventional method for fabricating a semiconductor device will be described with reference to the accompanying drawings.
FIG. 1a to FIG. 1d are sectional views illustrating process steps according to the first embodiment of a conventional method for fabricating a bipolar transistor.
In this embodiment, two NPN transistors are formed in one substrate.
As shown in FIG. 1a, an N.sup.+ conductive type first and second buried layers 13 and 13a are formed in a semiconductor substrate 11 of P-type conductivity by ion implantation. An epitaxial layer 15 of N-type conductivity is formed using the first and second buried layers 13 and 13a as a seed. An oxide film 17 is then grown on the semiconductor substrate 11. P-type conductive impurities are implanted into the epitaxial layer 15 between the first and second buried layers 13 and 13a to form isolation regions 19.
Subsequently, first and second collector regions 21 and 21a are formed by ion implantation, which are respectively connected to the first and second buried layers 13 and 13a. A first base region 23 is formed in the epitaxial layer 15 over the first buried layer 13. A second base region 23a is formed in the epitaxial layer 15 over the second buried layer 13a. In forming the base regions, the collector regions, and the isolation regions, impurity ions are implanted into the respective regions using masks different from one another (not shown).
As shown in FIG. 1b, the oxide film 17 on the first and second base regions 23 and 23a is selectively etched to define first and second emitter regions. The first emitter region is significantly wider than the second emitter region.
A polysilicon layer 25 is formed on an entire surface of the semiconductor substrate 11 including the oxide film 17. Impurity ions are implanted into the entire surface so that they are implanted into the first and second base regions 23 and 23a through the polysilicon layer 25.
The polysilicon layer 25 fills the hole in the oxide layer 17 corresponding to the smaller emitter region. The polysilicon layer 25 merely lines the hole in oxide layer 17 corresponding to the larger emitter region. As such, the walls 25a formed by the polysilicon layer 25 in the hole in the oxide layer 17 present a greater thickness through which to implant ions than does the floor 25b thereof.
Such a difference in the thickness of the polysilicon layer 25 causes the impurity ions to be implanted into the respective base regions at different depths, thereby creating a nonuniform emitter junction Ej.
As shown in FIG. 1c, a photoresist (not shown) is deposited on the polysilicon layer 25 and then patterned by exposure and developing processes. The polysilicon layer 25 is selectively removed by etching process using the patterned photoresist as a mask to form a first emitter poly 25a and a second emitter poly 25b.
As shown in FIG. 1d, an insulating layer 27 is formed on the entire surface of the semiconductor substrate 11 including the first and second polysilicon emitters 25a and 25b. A photoresist (not shown) is deposited on the insulating layer 27 and then patterned by exposure and developing processes. Surfaces of the first and second polysilicon emitters 25a and 25b are partially exposed by etching process using the patterned photoresist as a mask. The insulating layer 27 and the oxide film 17 are selectively removed to expose the surface of the semiconductor substrate 11 in the first and second base regions 23 and 23a and the first and second collector regions 21 and 21a. Subsequently, metal is deposited on the entire surface of the exposed semiconductor substrate 11 including the first and second emitter polys 25a and 25b and patterned to form metal patterns 29. As a result, the conventional method for fabricating the bipolar transistor according to the first embodiment is completed.
In the aforementioned embodiment, when the impurity ions are implanted for the emitter junctions through the polysilicon layer 25, distortion of the emitter junction occurs due to width difference between the first polysilicon emitter poly 25a and the second polysilicon emitter poly 25b.
To prevent the distortion of the emitter junction, a polysilicon layer in which impurity ions are doped is formed. However, such a polysilicon layer has a problem of complicating the overall process. For example, in the case that both an NPN transistor and a PNP transistor are formed in one substrate, a polysilicon layer having impurity ions of different conductivity types must be formed.
To solve such a problem, other conventional method for fabricating a semiconductor device will be described with reference to FIG. 2a to FIG. 2d. In this method, the NPN transistor and the PNP transistor are formed in one substrate.
As shown in FIG. 2a, first and second buried layers 13 and 13a are formed in a P-type semiconductor substrate 11. Here, each of the first buried layer 13 and the second buried layer 13a has N-type conductivity opposite to the semiconductor substrate 11.
Subsequently, first and second epitaxial layers 15 and 15a are grown using the first and second buried layers 13 and 13a as seeds. The first epitaxial layer 15 has N-type and is grown on the first buried layer 13, and the second epitaxial layer 15a has P-type and is grown on the second buried layer 13a.
Then, a plurality of oxide films 17 are formed by local oxidation of silicon (LOCOS) of the first and second epitaxial layers 15 and 15a. At this time, first and second collector regions, and first and second base regions are defined by the oxide films 17.
A second base region 23a is formed on the second epitaxial layer 15a down to a predetermined depth by N-type ion implantation. A first collector region 21 is also formed in the first epitaxial layer 15. A first base region 23 is then formed in the first epitaxial layer 15 down to a predetermined depth by P-type ion implantation. A second collector region 21a is also formed in the second epitaxial layer 15a. Here, the first collector region 21 is a collector region of the NPN transistor and is connected to the first buried layer 13. The second collector region 21a is a collector region of the PNP transistor and is connected to the second buried layer 13a.
As shown in FIG. 2b, a first chemical vapor deposition (CVD) oxide film 31 is deposited on an entire surface of the semiconductor substrate 11 including the oxide films 17. The first CVD oxide film 31 is selectively removed to expose the first and second base regions 23 and 23a. A P-type doped polysilicon layer 25 is formed on the entire surface including the exposed first and second base regions 23 and 23a. The polysilicon layer 25 is used as an emitter of the PNP transistor. Thus, an emitter junction can be formed at a portion with a predetermined depth, where the polysilicon layer 25 contacts with the second base region 23a.
As shown in FIG. 2c, a second CVD oxide film 31a is deposited on the entire surface of the semiconductor substrate 11 including the polysilicon layer 25. The second CVD oxide film 31a, at a portion where the NPN transistor will be formed, is then selectively removed so that the polysilicon layer 25 is partially exposed. N-type ions are implanted into the exposed polysilicon layer 25 and then annealing is performed. As a result, the emitter junction Ej is formed in the first base region 23.
As shown in FIG. 2d, the polysilicon layer 25 is patterned to form a first emitter 25a and a second emitter 25b. A third CVD oxide film 31b (not shown) is then deposited on the entire surface of the semiconductor substrate 11. The third CVD oxide film 31b is selectively removed to partially expose surfaces of the first and second emitters 25a and 25b. The third and second CVD oxide films 31b and 31a are selectively removed to expose the first and second base regions 23 and 23a as well as the first and second collector regions 21 and 21a. Finally, a metal is deposited on the semiconductor substrate 11 in the exposed first and second emitter polys 25a and 25b, the first and second base regions 23 and 23b, and the first and second collector regions 21 and 21a. The metal is then patterned to form metal patterns 29. As a result, the conventional method for fabricating the semiconductor device is completed.
The aforementioned conventional method for fabricating the semiconductor device has several problems.
First, the operating characteristic of the device deteriorates due to the difference between the current gain of the high current transistor having a wide emitter and current gain of the fast transistor having a wide emitter and the current gain of the fast transistor having a narrow emitter.
Second, in the case that the polysilicon (which is doped with impurities) is used to avoid nonuniformity of the emitter junction, the process steps become complicated.
Third, it is difficult to reduce difference in current gain between the high current transistor and the fast transistor even if the polysilicon which is doped with impurities is used and, at the same time, ion implantation is performed.
Finally, the metal has a poor topology due to step coverage between the polysilicon layer and the CVD oxide film.